FIG. 1 schematically illustrates an SRAM cell 110. The SRAM cell 110 comprises first and second drivers N1 and N2. Illustratively, the drivers N1 and N2 are pulldown NMOS devices N1 and N2. The source of N1 112 and the source of N2 114 are connected to a reference voltage Vss which, for example, is ground. The drain 116 of N2 is connected to the gate 118 of N1. The drain 120 of N1 is connected to the gate 122 of N2. The SRAM cell 10 of FIG. 1 also comprises two load devices L1 and L2. The load devices L1 and L2 each have one terminal 124, 126 connected to a supply voltage Vcc and another terminal 128, 130 connected to the drains 120, 116 of N1 and N2, respectively. The supply voltage Vcc is positive with respect to Vss.
The SRAM cell 110 also comprises two additional NMOS devices N3 and N4. The devices N3 and N4 are pass transistors. The gates 132, 134 of N3 and N4 are connected to a wordline whose signal value is designated WORD. The drains 136, 138 of N3 and N4 are connected to bit lines whose signal values are designated BIT and BIT, respectively. The sources 140, 142 of N3 and N4 are connected the drains 120, 116 of N1 and N2, respectively.
To write the cell, DATA (logic "1" or logic "0") is placed on the BIT line and DATA is placed on the BIT line. Then WORD is asserted. A read operation commences by precharging the BIT and BIT lines. The WORD line is asserted and either the BIT or BIT line will be discharged by one of the pull down transistors N1 or N2.
The purpose of the load devices L1 and L2 is to counteract the effect of charge leakage at the drains 120, 116 of N1 and N2. The load devices L1 and L2 may be polycrystalline silicon resistors.
A row 45 of SRAM cells 50 is shown in FIG. 2, where one of the SRAM cells 50 is shown in greater detail. The load devices of the SRAM cell 50 are polysilicon load resistors L.sub.1, and L.sub.2. Parasitic resistances Rvcc form the interconnect resistance between Vcc and the load devices L.sub.1 and L.sub.2 of the cells 50. As shown in FIG. 2, each cell 50 in the row 45 has associated with it an additional unit of parasitic resistance Rvcc. The Vcc interconnect parasitic resistance of each cell 50 is made up of one or more units of Rvcc as shown in FIG. 2. The actual voltage level of the "high" supply voltage received at the cell 50 will be much lower than Vcc if Rvcc is high or if the aggregate interconnect resistance from the Vcc pin to the cell 50 is high (i.e., if the total resistances of multiple internal parasitic resistances Rvcc from the Vcc pin to a specific cell 50 is high). Such a reduction in voltage level in the high supply voltage received at the cell 50 reduces the performance of the cell 50. Therefore, it is desirable for the Vcc interconnect resistance for each cell 50 to be as small as possible.
Lowering the value of the Vcc interconnect parasitic resistance Rvcc reduces the voltage drop between Vcc and the loads L.sub.1 and L.sub.2. This enhances circuit operation and reduces wasted power.
FIG. 3 shows a structure used to implement one leg of a conventional SRAM structure such as shown in FIG. 1. The structure 1 of FIG. 3 comprises a substrate 10 which is, for example, a P-type substrate. A driver device 12 is formed in the substrate 10. The driver device 12 is an NMOSFET and comprise N+ type drain region 14 and N+ type source region 16 which are separated by a channel 18. A thin gate oxide layer 20 is formed over the channel 18. A polysilicon gate 22 is formed over the gate oxide 20.
An inter-poly-dielectric layer (IPD) 30 is formed over the driver device 12. The (IPD) layer has a thickness of 1500.ANG.-2000.ANG.. A thick polysilicon layer 80 is formed on the IPD layer 30. A region 82 of the polysilicon layer 80 is heavily doped (N+ type) to form a low resistance Vcc interconnect. A region 84 of the layer 80 is heavily doped (N+ type) to form a low resistance interconnect to the drain region 14 of the driver device. This driver interconnect (also known as poly-2/poly-1 via) extends through a via opening 32 in the IPD layer 30. A region 86 of the polysilicon layer 80 is lightly doped (N- type) to form a poly-load resistance region. (There is also an additional via opening in the IPD layer 30 (not shown) for connecting the interconnect 84 to the gate of another driver.)
A problem with this structure is lateral diffusion from the heavily doped regions 82 and 84 into the lightly doped region 86.
Accordingly, it is an object of the invention to provide an SRAM cell with a poly-load resistor structure which overcomes the problems of the prior art.
Specifically, it is an object of the invention to provide an SRAM cell with a poly-load resistor structure in which lateral diffusion from highly doped interconnect regions into a lightly doped poly-load region is reduced. It is also an object of the invention to provide a method for fabricating such a poly-load resistor structure without increasing the number of photolithographic steps over the number of photolithographic steps used in the prior art.